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2GB - 2x128Mx72 SDRAM, REGISTERED
FEATURES
Burst Mode Operation Auto and Self Refresh capability LVTTL compatible inputs and outputs Serial Presence Detect with EEPROM Fully synchronous: All signals are registered on the positive edge of the system clock Programmable Burst Lengths: 1, 2, 4, 8 or Full Page 3.3V 0.3V Power Supply Dual Rank 168 Pin DIMM JEDEC * PCB - AD2: 28.58mm (1.125") TYP
WV3DG72256V-AD2
PRELIMINARY
DESCRIPTION
The WV3DG72256V is a 2x128Mx72 synchronous DRAM module which consists of eighteen 256Mx4 stack SDRAM components (stacked from 128Mx4) in TSOP II package, two 18 bit Drive ICs for input control signal and one 2Kb EEPROM in an 8 pin TSSOP package for Serial Presence Detect which are mounted on a 168 pin DIMM multilayer FR4 Substrate.
* This product is under development, is not qualified or characterized and is subject to change without notice. NOTE: Consult factory for availability of: * RoHS compliant products * Vendor source control options * Industrial temperature option
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 FRONT VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 CB0 CB1 VSS NC NC VCC WE# DQM0 PIN 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 BACK DQM1 CS0# NC VSS A0 A2 A4 A6 A8 A10/AP BA1 VCC VCC CLK0 VSS NC CS2# DQM2 DQM3 NC VCC NC NC CB2 CB3 VSS DQ16 DQ17 PIN 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 FRONT DQ18 DQ19 VCC DQ20 NC *VREF *CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS NC NC WP SDA SCL VCC PIN 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 BACK VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 CB4 CB5 VSS NC NC VCC CAS# DQM4 PIN 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 BACK DQM5 CS1# RAS# VSS A1 A3 A5 A7 A9 BA0 A11 VCC NC A12 VSS CKE0 CS3# DQM6 DQM7 NC VCC NC NC CB6 CB7 VSS DQ48 DQ49 PIN 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 BACK DQ50 DQ51 VCC DQ52 NC *VREF REGE VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS NC NC SA0 SA1 SA2 VCC
PIN NAMES
A0 - A12 BA0-1 DQ0-63 CB0-7 CLK0 CKE0 CS0# - CS3# RAS# CAS# WE# DQM0-7 VCC VSS VREF REGE SDA SCL SA0-2 NC Address Input (Multiplexed) Select Bank Data Input/Output Check Bit (Data-In/Data-Out) Clock Input Clock Enable Input Chip Select Input Row Address Strobe Column Address Strobe Write Enable DQM Power Supply (3.3V) Ground Power Supply for Reference Register Enable Serial Data I/O Serial Clock Address in EEPROM No Connect
* Pins not used in this module.
January 2006 Rev. 0
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FUNCTIONAL BLOCK DIAGRAM
BCS1#, B2CKE0 BCS0#, B0CKE0 PCLK0 B0RAS#, B0CAS#, B0WE#, B0BA0, B0BA1 B0A0~B0A12 BDQM0 DQ0~3 10 PCLK1 CLK# CS1, CKE CTL Add DQM DQ0~3 CLK# CS1, CKE CTL Add DQM DQ0~3 CLK# CS1, CKE CTL Add DQM DQ0~3 CLK# CS1, CKE CTL Add DQM DQ0~3 CLK# CS1, CKE CTL Add DQM DQ0~3 CLK# CS0, CKE CTL Add DQM DQ0~3 CLK# CS0, CKE CTL Add DQM DQ0~3 CLK# CS0, CKE CTL Add DQM DQ0~3 CLK# CS0, CKE CTL Add DQM DQ0~3 CLK# CS0, CKE CTL Add DQM DQ0~3
WV3DG72256V-AD2
PRELIMINARY*
BDQM4 DQ32~35 10
CLK# CS0, CKE CTL Add DQM DQ0~3 CLK# CS0, CKE CTL Add DQM DQ0~3 10 CLK# CS0, CKE CTL Add DQM DQ0~3 10 CLK# CS0, CKE CTL Add DQM DQ0~3 10 CLK# CS0, CKE CTL Add DQM DQ0~3 10
CLK# CS1, CKE CTL Add DQM DQ0~3 CLK# CS1, CKE CTL Add DQM DQ0~3 CLK# CS1, CKE CTL Add DQM DQ0~3 CLK# CS1, CKE CTL Add DQM DQ0~3 CLK# CS1, CKE CTL Add DQM DQ0~3
DQ0~7 10 PCLK2
DQ36~39
DQ0~11 10 PCLK3
BDQM5 DQ40~43
DQ0~15 10 PCLK4
DQ44~47
CB0~3 10 BCS3#, B3CKE0 BCS2, B1CKE0 PCLK5
DQ4~7
BDQM2 DQ16~19 10 PCLK6
CLK# CS1, CKE CTL Add DQM DQ0~3 CLK# CS1, CKE CTL Add DQM DQ0~3 CLK# CS1, CKE CTL Add DQM DQ0~3 CLK# CS1, CKE CTL Add DQM DQ0~3
CLK# CS0, CKE CTL Add DQM DQ0~3 CLK# CS0, CKE CTL Add DQM DQ0~3 CLK# CS0, CKE CTL Add DQM DQ0~3 CLK# CS0, CKE CTL Add DQM DQ0~3
BDQM6 DQ48~51 10
CLK# CS0, CKE CTL Add DQM DQ0~3 CLK# CS0, CKE CTL Add DQM DQ0~3
CLK# CS1, CKE CTL Add DQM DQ0~3 CLK# CS1, CKE CTL Add DQM DQ0~3 CLK# CS1, CKE CTL Add DQM DQ0~3 CLK# CS1, CKE CTL Add DQM DQ0~3
DQ20~23 10 PCLK7
DQ52~55 10
BDQM3 DQ24~27 10 PCLK8 B1RAS#, B1CAS#, B1WE#, B1BA0, B1BA1 B1A0~B1A12 DQ28~31
DQ56~59 10
CLK# CS0, CKE CTL Add DQM DQ0~3 CLK# CS0, CKE CTL Add DQM DQ0~3 VSS
DQ60~63 10
VCC
IY0 IY1 IY2 IY3 IY4 IY5 IY6 IY7 IY8 IY9 PCLK0 PCLK1 PCLK2 PCLK3 PCLK4 PCLK5 PCLK6 PCLK7 PCLK8 PCLK9
CLK1,2,3
10 12pF
VCC 10k PCLK9 REGE A11, A12, BA1 CS2#, CS3# CKE0 DQM2, 3, 6, 7
74ALVCF162835
LE
OE# B0A11, B0A12, B0BA1 B1A11, B1A12, B1BA1 BCS2, BCS3 B0CKE0, B1CKE0 B2CKE0,B3CKE0 DQM2, 3, 6, 7
CLK0,2,3
10 12pF
CLK FBIN Cb
*1
G AGND AVCC
CDCF2510 Serial PD SCL WP 47K
A3~A10, BA0
B0A3~B0A10, B0BA0 B1A3~B1A10, B1BA0
FBOUT
74ALVCF162835
Note 1. The actual values of Cb will depend upon the PLL chosen.
LE A0, A1, A2 RAS#, CAS#, WE# CS0#, CS1# DQM0, 1, 4, 5
OE# B0A0, B0A1, B0BA2 B1A0, B1A1,B1BA2 B0RAS#, BCAS#, B0WE# B1RAS#, BCAS#, B1WE# BCS0, BCS1 DQM0, 1, 4, 5 SDA A0 SA0 A1 SA1 A2 SA2
74ALVCF162835
LE
OE#
January 2006 Rev. 0
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ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Current Symbol VIN, VOUT VCC, VCCQ TSTG PD IOS Value
WV3DG72256V-AD2
PRELIMINARY*
Units V V C W mA
-1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 36 50
Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
Voltage Referenced to: VSS = 0V, 0C TA 70
Parameter Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Symbol VCC VIH VIL VOH VOL ILI Min 3.0 2.0 -0.3 2.4 -- -10 Typ 3.3 3.0 -- -- -- -- Max 3.6 VCCQ+0.3 0.8 -- 0.4 10 Unit V V V V V A 1 2 IOH= -2mA IOL= -2mA 3 Note
Note: 1. VIH (max)= 5.6V AC. The overshoot voltage duration is 3ns. 2. VIL (min)= -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VCCQ Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
TA = 25 C, f = 1MHz, VCC = 3.3V, VREF = 1.4V 200mV
Parameter Input Capacitance (A0-A12, BA0-BA1) Input Capacitance (RAS#, CAS#, WE#) Input Capacitance (CKE0) Input Capacitance (CLK0) Input Capacitance (CS0# - CS3#) Input Capacitance (DQM0-DQM7) Data input/output capacitance (DQ0-DQ63), (CB0-BC7) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 COUT Max 15 15 15 20 15 15 22 Unit pF pF pF pF pF pF pF
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VCC = 3.3V, 0C TA 70C
Parameters Operating Current (One bank active) Precharge Standby Current in Power Down Mode Precharge Standby Current in Non-Power Down Mode Symbol Burst Length = 1 tRC tRC(min) IOL = 0mA CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC =10ns Input signals are charged one time during 20 CKE VIH(min), CLK VIL(max), tCC= Input signals are stable CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are charged one time during 20ns CKE VIH(min), CLK VIL(max), tCC = input signals are stable Io = mA Page burst 4 Banks activated tCCD = 2CLK tRC tRC(min) CKE 0.2V Conditions
WV3DG72256V-AD2
PRELIMINARY*
OPERATING CURRENT CHARACTERISTICS
Versions 133/100 2,520 530 130 1,170 410 670 270 1,530 950
Units
Note
ICC1 ICC2P ICC2PS ICC2N ICC2NS
mA mA mA mA mA mA mA mA mA
1
Active standby current in power-down mode
ICC3P ICC3PS ICC3N
Active standby in current non powerdown mode ICC3NS
Operating current (Burst mode)
ICC4
2,610
mA
1
Refresh current Self refresh current
Notes: 1. Measured with outputs open. 2. Refresh period is 64ms.
ICC5 ICC6
4,590 420
mA mA
2
January 2006 Rev. 0
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AC OPERATING TEST CONDITIONS
VCC = 3.3V, 0C TA 70C
Parameter AC Input level (VIN/VIL) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2
WV3DG72256V-AD2
PRELIMINARY*
Units V V ns V
3.3V
VTT=1.4V
1220 Output 870 50pF VOH (DC)=2.4V, IOH=-2mA VOL (DC)=2.4V, IOL=-2mA Output Z0 = 50
50
50pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
AC OPERATING TEST CONDITIONS
Parameter Row active to row active delay RAS# to CAS# delay Row Precharge time Row active time Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data Symbol tRRD(MIN) tRCD(MIN) tRP(MIN) tRAS(MIN) tRAS(MAX) tRC(MIN) tRDL(MIN) tDAL(MIN) tCDL(MIN) tBDL(MIN) tCCD(MIN) CAS Latency = 3 Cas Latency = 2 Value 133/100 15 20 20 45 100 65 2 2 CLK + tRP 1 1 1 2 1 Units ns ns ns ns s ns CLK -- CLK CLK CLK CLK ea 1 2 2 3 4 1 2 Notes 1 1 1 1
Notes: 1. The minimum number of clock cycles is determined by driving the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop.
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OPERATING AC PARAMETER
133/100 Parameter CLK cycle time CLK to valid output delay Output data hold time CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-z CLK to output in Hi-z CAS latency = 3 CAS latency = 2 CAS latency = 3 CAS latency = 2 CAS latency = 3 CAS latency = 2 CAS latency = 3 CAS latency = 2 Symbol tCC tSAC tOH tCH tCL tSS tSH tSLZ tHZ 3 - 2.5 2.5 1.5 0.8 1 Min 7.5 -
WV3DG72256V-AD2
PRELIMINARY*
Max 1,000 5.4 -
Units ns ns ns ns ns ns ns ns
Notes 1 1, 2 2 3 3 3 3 2
5.4 -
ns
Notes: 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr &tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr = tf)/2-1]ns should be added to the parameter.
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ORDERING INFORMATION FOR AD2
Part Number WV3DG72256V10AD2xx WV3DG72256V7AD2xx WV3DG72256V75AD2xx Clock Speed 100MHz 133MHz 133MHz CAS Latency CL=2 CL=2 CL=3
WV3DG72256V-AD2
PRELIMINARY*
Height* 28.58 (1.25") TYP 28.58 (1.25") TYP 28.58 (1.25") TYP
NOTES: * Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant) * Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) * Consult factory for availability of industrial temperature (-40C to 85C) option
PACKAGE DIMENSIONS FOR AD2
133.350 5.250 3.00 0.118 127.350 5.014 1.372 0.054 2.000 0.079 0.157 0.004 (4.000 0.100)
3.000 0.118 17.780 0.700
28.575 TYP 1.125
118DIA 0.004 3.000DIA 0.100 8.890 0.350
6.350 0.250 11.430 (0.450) 36.830 1.450 115.57 4.550
6.350 0.250 54.64 2.150
2.540 Min 0.100 Min
?
8.86 Max (0.270 Max)
0.165 Min 4.19 Min
1.2700.10 0.0500.0039
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
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PART NUMBERING GUIDE
WV3DG72256V-AD2
PRELIMINARY*
WV 3 D G 72 256 V xx AD2 I- x G
WEDC MEMORY SDRAM GOLD BUS WIDTH DEPTH 3.3 VOLTS CLOCK SPEED (MHz) 10 = 100MHz @ CL = 2 7 = 133MHz @ CL = 2 75 = 133MHz @ CL = 3 PACKAGE 168 PIN DIMM AD2: 28.58mm (1.125") INDUSTRIAL TEMP COMPONENT VENDOR NAME (M = Micron) (S = Samsung) G = ROHS COMPLIANT
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Document Title
2GB- 2x128Mx72 SDRAM, REGISTERED
WV3DG72256V-AD2
PRELIMINARY*
Revision History Rev #
Rev 0
History
Created Data sheet
Release Date
January 2006
Status
Advanced
January 2006 Rev. 0
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White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com

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